1. Field of Invention
The present invention relates to a semiconductor device and an operating method thereof. More specifically, the present invention relates to a semiconductor device for improving reliability of an erase operation and an operating method thereof.
2. Description of the Related Art
A semiconductor device includes a memory cell array composed of a plurality of cell blocks, and a plurality of peripheral circuits for storing data in the memory cell array, or reading or erasing the stored data.
The peripheral circuit includes a low decoder that selects one cell block from the plurality of cell blocks included in the memory cell array, and transmits an operation voltage to word lines of the selected cell block; a voltage generation circuit that generates an operation voltage in accordance with a programming command, a read command, or an erase command and transmits the generated programming command and read or erase command to the low decoder; a plurality of page buffers that are connected to bit lines of the memory cell array to change potentials of the bit lines at the time of reading or erasing or detect changes in the potentials of the bit lines; a column selection circuit that selects the page buffer in accordance with a column address and transmits program data to the selected page buffer or receives data from the selected page buffer; an input/output circuit that inputs and outputs data; and a control circuit that controls the low decoder, the voltage generation circuit, the page buffer, the column selection circuit, and the input/output circuit.
The semiconductor device including the above-described circuits performs a program, a read operation, or an erase operation in accordance with an operation command and an address, where the operation command may be input to the control circuit. Of these, the erase operation will be described as follows.
The erase operation is performed in an incremental step pulse erase (ISPE) scheme that gradually increases an erase voltage. When the erase operation starts, all memory cells included in the selected cell blocks are erased by applying a ground voltage (0 V) to the word lines of the selected cell block, and applying an erase voltage to a well of the selected cell block.
Subsequently, an erase verification operation is performed to determine whether threshold voltages of all of the memory cells included in the selected cell block are reduced to an erase reference voltage. When the threshold voltages of all of the memory cells included in the selected cell block have reached the erase reference voltage based as shown by a result of the erase verification operation, the erase operation with respect to the selected cell block is terminated. If there are memory cells which have not reached the erase reference voltage, the erase operation is repeatedly performed while gradually increasing the erase voltage until the threshold voltages of all of the memory cells of the selected cell block have reached the erase reference voltage.
Among the above-described operations, with regard to the erase verification operation, the selected bit lines are precharged, and then the selected cells are determined as cells which are not erased when a current of the bit line that is changed in accordance with turn-on or turn-off of the memory cell is higher than a fixed sensing reference level after having been subjected to the erase operation. The selected cells are determined as cells which are erased when the current is lower than the sensing reference level.
Meanwhile, electrical characteristics of the semiconductor device are gradually deteriorated when the semiconductor device is used, and particularly, deterioration occurs in a junction of the memory cells, and therefore an amount of current passing through the junction may be gradually reduced. If electrical characteristics of the semiconductor device have deteriorated, a current that can be measured when performing an erase verification operation becomes higher than the sensing reference level even when the same erase operation is performed, and therefore the cells which are completely erased may be erroneously determined as program cells (cells which are not completely erased), thereby reducing reliability of the semiconductor device.